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Electrical Specifications Subject to Change
LTC2142-12/ LTC2141-12/LTC2140-12 12-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs DESCRIPTION
The LTC(R)2142-12/LTC2141-12/LTC2140-12 are 2-channel simultaneous sampling 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 70.8dB SNR and 89dB spurious free dynamic range (SFDR). Ultralow jitter of 0.08psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include 0.3LSB INL (typ), 0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is 0.3LSBRMS. The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V. The ENC+ and ENC- inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
FEATURES
n n n n n n n n n n n n n
2-Channel Simultaneously Sampling ADC 70.8dB SNR 89dB SFDR Low Power: 92mW/65mW/48mW Total 46mW/33mW/24mW per Channel Single 1.8V Supply CMOS, DDR CMOS, or DDR LVDS Outputs Selectable Input Ranges: 1VP-P to 2VP-P 800MHz Full Power Bandwidth S/H Optional Data Output Randomizer Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Serial SPI Port for Configuration 64-Pin (9mm x 9mm) QFN Package
APPLICATIONS
n n n n n n
Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multi-Channel Data Acquisition Nondestructive Testing
TYPICAL APPLICATION
1.8V VDD 1.8V OVDD
2-Tone FFT, fIN = 70MHz and 69MHz
0 -10 -20 AMPLITUDE (dBFS)
CH 1 ANALOG INPUT
S/H
12-BIT ADC CORE
D1_11 * * * D1_0 OUTPUT DRIVERS D2_11 * * * D2_0
-30 -40 -50 -60 -70 -80 CMOS OR LVDS OUTPUTS
CH 2 ANALOG INPUT
S/H
12-BIT ADC CORE
-90 -100 -110 -120
65MHz CLOCK
CLOCK CONTROL
21421012 TA01a
0
20 10 FREQUENCY (MHz)
30
21821012 TA01b
GND
OGND
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LTC2142-12/ LTC2141-12/LTC2140-12 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages (VDD, OVDD) ....................... -0.3V to 2V Analog Input Voltage (AIN+, AIN -, PAR/SER, SENSE) (Note 3) .......... -0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC-, CS, SDI, SCK) (Note 4) .................................... -0.3V to 3.9V SDO (Note 4)............................................. -0.3V to 3.9V
Digital Output Voltage ................ -0.3V to (OVDD + 0.3V) Operating Temperature Range LTC2142C, LTC2141C, LTC2140C ............. 0C to 70C LTC2142I, LTC2141I, LTC2140I ............-40C to 85C Storage Temperature Range .................. -65C to 150C
PIN CONFIGURATIONS
FULL RATE CMOS OUTPUT MODE TOP VIEW 64 VDD 63 SENSE 62 VREF 61 SDO 60 OF1 59 OF2 58 D1_11 57 D1_10 56 D1_9 55 D1_8 54 D1_7 53 D1_6 52 D1_5 51 D1_4 50 D1_3 49 D1_2 DOUBLE DATA RATE CMOS OUTPUT MODE TOP VIEW 64 VDD 63 SENSE 62 VREF 61 SDO 60 OF2_1 59 DNC 58 D1_10_11 57 DNC 56 D1_8_9 55 DNC 54 D1_6_7 53 DNC 52 D1_4_5 51 DNC 50 D1_2_3 49 DNC 48 D1_1 47 D1_0 46 DNC 45 DNC 44 DNC 43 DNC 42 OVDD 41 OGND 40 CLKOUT+ 39 CLKOUT- 38 D2_11 37 D2_10 36 D2_9 35 D2_8 34 D2_7 33 D2_6 VDD 1 VCM1 2 GND 3 AIN1+ 4 AIN1- 5 GND 6 REFH 7 REFL 8 REFH 9 REFL 10 PAR/SER 11 AIN2+ 12 AIN2- 13 GND 14 VCM2 15 VDD 16 65 GND 48 D1_0_1 47 DNC 46 DNC 45 DNC 44 DNC 43 DNC 42 OVDD 41 OGND 40 CLKOUT+ 39 CLKOUT- 38 D2_10_11 37 DNC 36 D2_8_9 35 DNC 34 D2_6_7 33 DNC TJMAX = 150C, JA = 29C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB VDD 17 ENC+ 18 ENC- 19 CS 20 SCK 21 SDI 22 DNC 23 DNC 24 DNC 25 DNC 26 DNC 27 D2_0_1 28 DNC 29 D2_2_3 30 DNC 31 D2_4_5 32 UP PACKAGE 64-LEAD (9mm 9mm) PLASTIC QFN
VDD 1 VCM1 2 GND 3 AIN1+ 4 AIN1- 5 GND 6 REFH 7 REFL 8 REFH 9 REFL 10 PAR/SER 11 AIN2+ 12 AIN2- 13 GND 14 VCM2 15 VDD 16
65 GND
TJMAX = 150C, JA = 29C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB DOUBLE DATA RATE LVDS OUTPUT MODE
VDD 17 ENC+ 18 ENC- 19 CS 20 SCK 21 SDI 22 DNC 23 DNC 24 DNC 25 DNC 26 D2_0 27 D2_1 28 D2_2 29 D2_3 30 D2_4 31 D2_5 32 UP PACKAGE 64-LEAD (9mm x 9mm) PLASTIC QFN
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LTC2142-12/ LTC2141-12/LTC2140-12 PIN CONFIGURATIONS
DOUBLE DATA RATE LVDS OUTPUT MODE TOP VIEW 64 VDD 63 SENSE 62 VREF 61 SDO 60 OF2_1+ 59 OF2_1- 58 D1_10_11+ 57 D1_10_11- 56 D1_8_9+ 55 D1_8_9- 54 D1_6_7+ 53 D1_6_7- 52 D1_4_5+ 51 D1_4_5- 50 D1_2_3+ 49 D1_2_3- VDD 1 VCM1 2 GND 3 AIN1+ 4 AIN1- 5 GND 6 REFH 7 REFL 8 REFH 9 REFL 10 PAR/SER 11 AIN2+ 12 AIN2- 13 GND 14 VCM2 15 VDD 16 65 GND 48 D1_0_1+ 47 D1_0_1- 46 DNC 45 DNC 44 DNC 43 DNC 42 OVDD 41 OGND 40 CLKOUT+ 39 CLKOUT- 38 D2_10_11+ 37 D2_10_11- 36 D2_8_9+ 35 D2_8_9- 34 D2_6_7+ 33 D2_6_7- TJMAX = 150C, JA = 29C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC2142CUP-12#PBF LTC2142IUP-12#PBF LTC2141CUP-12#PBF LTC2141IUP-12#PBF LTC2140CUP-12#PBF LTC2140IUP-12#PBF TAPE AND REEL LTC2142CUP-12#TRPBF LTC2142IUP-12#TRPBF LTC2141CUP-12#TRPBF LTC2141IUP-12#TRPBF LTC2140CUP-12#TRPBF LTC2140IUP-12#TRPBF PART MARKING* LTC2142UP-12 LTC2142UP-12 LTC2141UP-12 LTC2141UP-12 LTC2140UP-12 LTC2140UP-12 PACKAGE DESCRIPTION 64-Lead (9mm x 9mm) Plastic QFN 64-Lead (9mm x 9mm) Plastic QFN 64-Lead (9mm x 9mm) Plastic QFN 64-Lead (9mm x 9mm) Plastic QFN 64-Lead (9mm x 9mm) Plastic QFN 64-Lead (9mm x 9mm) Plastic QFN TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
VDD 17 ENC+ 18 ENC- 19 CS 20 SCK 21 SDI 22 DNC 23 DNC 24 DNC 25 DNC 26 D2_0_1- 27 D2_0_1+ 28 D2_2_3- 29 D2_2_3+ 30 D2_4_5- 31 D2_4_5+ 32 UP PACKAGE 64-LEAD (9mm 9mm) PLASTIC QFN
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LTC2142-12/ LTC2141-12/LTC2140-12 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Note 5)
LTC2142-12 PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Gain Matching Offset Matching Transition Noise Internal Reference External Reference Differential Analog Input (Note 7) Internal Reference External Reference CONDITIONS
l
LTC2141-12 MIN 12 TBD -1 -9 -2.1 TYP 0.3 0.1 1.5 1.5 -0.6 10 30 10 0.3 1.5 0.3 MAX TBD 1 9 0.9 12
LTC2140-12 MIN TBD -1 -9 -2.1 TYP 0.3 0.1 1.5 1.5 -0.6 10 30 10 0.3 1.5 0.3 MAX TBD 1 9 0.9 UNITS Bits LSB LSB mV %FS %FS V/C ppm/C ppm/C %FS mV LSBRMS
MIN 12 TBD -1 -9 -2.1
TYP 0.3 0.1 1.5 1.5 -0.6 10 30 10 0.3 1.5 0.3
MAX TBD 1 9 0.9
Differential Analog Input (Note 6) l
l l l
ANALOG INPUT
SYMBOL PARAMETER VIN VIN(CM) VSENSE IINCM
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS 1.7V < VDD < 1.9V Differential Analog Input (Note 8) Per Pin, 65Msps Per Pin, 40Msps Per Pin, 25Msps 0 < AIN+, AIN- < VDD 0 < PAR/SER < VDD 0.625 < SENSE < 1.3V Single-Ended Encode Differential Encode Figure 6 Test Circuit
l l l l l l
MIN 0.7 0.625
TYP 1 to 2 VCM 1.250 81 50 31
MAX 1.25 1.300
UNITS VP-P V V A A A
Analog Input Range (AIN+ - AIN-) Analog Input Common Mode (AIN+ + AIN-)/2 Analog Input Common Mode Current
External Voltage Reference Applied to SENSE External Reference Mode
IIN1 IIN2 IIN3 tAP tJITTER CMRR BW-3B
Analog Input Leakage Current (No Encode) PAR/SER Input Leakage Current SENSE Input Leakage Current Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Jitter Analog Input Common Mode Rejection Ratio Full-Power Bandwidth
-1 -3 -6 0 0.08 0.10 80 800
1 3 6
A A A ns psRMS psRMS dB MHz
21421012p
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LTC2142-12/ LTC2141-12/LTC2140-12
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 5)
LTC2142-12 SYMBOL SNR PARAMETER Signal-to-Noise Ratio CONDITIONS 5MHz Input 30MHz Input 70MHz Input 140MHz Input
l
DYNAMIC ACCURACY
LTC2141-12 MIN TBD TYP 70.5 70.5 70.4 70.2 89 89 88 84 95 95 95 95 70.4 70.4 70.3 69.9 -110 MAX
LTC2140-12 MIN TBD TYP 71 71 70.9 70.7 89 89 88 84 95 95 95 95 70.9 70.9 70.8 70.4 -110 MAX UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc
MIN TBD
TYP 70.8 70.8 70.7 70.5 89 89 88 84 95 95 95 95 70.7 70.7 70.6 70.2 -110
MAX
SFDR
Spurious Free Dynamic Range 5MHz Input 2nd or 3rd Harmonic 30MHz Input 70MHz Input 140MHz Input Spurious Free Dynamic Range 5MHz Input 4th Harmonic or Higher 30MHz Input 70MHz Input 140MHz Input
l
TBD
TBD
TBD
l
TBD
TBD
TBD
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
5MHz Input 30MHz Input 70MHz Input 140MHz Input 10MHz Input
l
TBD
TBD
TBD
Crosstalk
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER VCM Output Voltage VCM Output Temperature Drift VCM Output Resistance VREF Output Voltage VREF Output Temperature Drift VREF Output Resistance VREF Line Regulation -400A < IOUT < 1mA 1.7V < VDD < 1.9V -600A < IOUT < 1mA IOUT = 0 CONDITIONS IOUT = 0
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
MIN 0.5 * VDD - 25mV TYP 0.5 * VDD 25 4 1.225 1.250 25 7 0.6 1.275 MAX 0.5 * VDD + 25mV UNITS V ppm/C V ppm/C mV/V
21421012p
5
LTC2142-12/ LTC2141-12/LTC2140-12 DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER ENCODE INPUTS (ENC+, ENC- ) Differential Encode Mode (ENC- Not Tied to GND) VID VICM VIN RIN CIN VIH VIL VIN RIN CIN VIH VIL IIN CIN ROL IOH COUT Differential Input Voltage Common Mode Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance Logic Low Output Resistance to GND Logic High Output Leakage Current Output Capacitance (Note 8) Internally Set Externally Set (Note 8) ENC+, ENC- to GND (See Figure 10) (Note 8) VDD = 1.8V VDD = 1.8V ENC+ to GND (See Figure 11) (Note 8) VDD = 1.8V VDD = 1.8V VIN = 0V to 3.6V (Note 8) VDD = 1.8V, SDO = 0V SDO = 0V to 3.6V (Note 8)
l l l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS MIN TYP MAX UNITS
0.2 1.2 1.1 0.2 10 3.5 1.2 0.6 0 30 3.5 1.3 0.6 -10 3 200 -10 3 10 10 3.6 1.6 3.6
V V V V k pF V V V k pF V V A pF A pF
Single-Ended Encode Mode (ENC- Tied to GND)
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE) OVDD = 1.8V VOH VOL VOH VOL VOH VOL VOD VOS RTERM High Level Output Voltage Low Level Output Voltage High Level Output Voltage Low Level Output Voltage High Level Output Voltage Low Level Output Voltage Differential Output Voltage Common Mode Output Voltage On-Chip Termination Resistance IO = -500A IO = 500A IO = -500A IO = 500A IO = -500A IO = 500A 100 Differential Load, 3.5mA Mode 100 Differential Load, 1.75mA Mode 100 Differential Load, 3.5mA Mode 100 Differential Load, 1.75mA Mode Termination Enabled, OVDD = 1.8V
l l l l
1.750
1.790 0.010 1.488 0.010 1.185 0.010 0.050
V V V V V V 454 1.375 mV mV V V
OVDD = 1.5V
OVDD = 1.2V
DIGITAL DATA OUTPUTS (LVDS MODE) 247 1.125 350 175 1.250 1.250 100
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LTC2142-12/ LTC2141-12/LTC2140-12 POWER REQUIREMENTS
SYMBOL PARAMETER VDD OVDD IVDD IOVDD PDISS Analog Supply Voltage Output Supply Voltage Analog Supply Current Digital Supply Current Power Dissipation CONDITIONS (Note 10) (Note 10) DC Input Sine Wave Input Sine Wave Input, OVDD = 1.2V
l DC Input Sine Wave Input, OVDD = 1.2V l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 9)
LTC2142-12 MIN 1.7 1.1 TYP 1.8 1.8 50.9 51.3 3.8 91.6 96.9 1.7 1.7 1.8 1.8 52.6 53.8 30 57.4 149 200 1 10 20 TBD MAX 1.9 1.9 TBD MIN 1.7 1.1 CMOS Output Modes: Full Data Rate and Double Data Rate 1.8 1.8 35.9 36.2 2.4 64.6 68 1.7 1.7 1.8 1.8 37.4 38.7 29.6 57.1 121 172 1 10 20 TBD 1.9 1.9 TBD 1.7 1.1 1.8 1.8 26.9 27 1.5 48.4 50.4 1.7 1.7 1.8 1.8 28.3 29.5 29.3 56.8 104 155 1 10 20 TBD 1.9 1.9 TBD V V mA mA mA mW mW V V mA mA mA mA mW mW mW mW mW LTC2141-12 TYP MAX LTC2140-12 MIN TYP MAX UNITS
LVDS Output Mode VDD OVDD IVDD IOVDD PDISS Analog Supply Voltage Output Supply Voltage Analog Supply Current Digital Supply Current (0VDD = 1.8V) Power Dissipation (Note 10) (Note 10) Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode
l l l l l
1.9 1.9 TBD TBD TBD
1.9 1.9 TBD TBD TBD
1.9 1.9 TBD TBD TBD
All Output Modes PSLEEP PNAP PDIFFCLK Sleep Mode Power Nap Mode Power Power Increase with Differential Encode Mode Enabled (No Increase for Nap or Sleep Modes)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
LTC2142-12 SYMBOL fS tL tH tAP PARAMETER Sampling Frequency ENC Low Time (Note 8) ENC High Time (Note 8) Sample-and-Hold Acquisition Delay Time PARAMETER ENC to Data Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Pipeline Latency CONDITIONS CL = 5pF (Note 8) CL = 5pF (Note 8) tD - tC (Note 8) Full Data Rate Mode Double Data Rate Mode
l l l
TIMING CHARACTERISTICS
CONDITIONS (Note 10)
LTC2141-12 MIN 1 11.88 2 11.88 2 12.5 12.5 12.5 12.5 0 TYP MAX 40 500 500 500 500 65 1 19 2 19 2
LTC2140-12 MIN TYP 20 20 20 20 0 MAX 25 500 500 500 500 UNITS MHz ns ns ns ns ns
MIN
l l l l l
TYP 7.69 7.69 7.69 7.69 0
MAX 500 500 500 500
1 7.3 2 7.3 2
Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On
SYMBOL tD tC tSKEW
MIN 1.1 1 0
TYP 1.7 1.4 0.3 6 6.5
MAX 3.1 2.6 0.6
UNITS ns ns ns Cycles Cycles
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
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LTC2142-12/ LTC2141-12/LTC2140-12 TIMING CHARACTERISTICS
SYMBOL tD tC tSKEW PARAMETER ENC to Data Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Pipeline Latency SPI Port Timing (Note 8) tSCK tS tH tDS tDH tDO SCK Period CS to SCK Setup Time SCK to CS Setup Time SDI Setup Time SDI Hold Time SCK Falling to SDO Valid Readback Mode, CSDO = 20pF RPULLUP = 2k , Write Mode Readback Mode, CSDO = 20pF RPULLUP = 2k ,
l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS CL = 5pF (Note 8) CL = 5pF (Note 8) tD - tC (Note 8)
l l l
MIN 1.1 1 0
TYP 1.8 1.5 0.3 6.5
MAX 3.2 2.7 0.6
UNITS ns ns ns Cycles ns ns ns ns ns ns
Digital Data Outputs (LVDS Mode)
40 250 5 5 5 5 125
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2142), 40MHz (LTC2141), or 25MHz (LTC2140), LVDS outputs, differential ENC+/ENC- = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from -0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2's complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: VDD = 1.8V, fSAMPLE = 65MHz (LTC2142), 40MHz (LTC2141), or 25MHz (LTC2140), CMOS outputs, ENC+ = single-ended 1.8V square wave, ENC- = 0V, input range = 2VP-P with differential drive, 5pF load on each digital output unless otherwise noted. The supply current and power dissipation specifications are totals for the entire IC, not per channel. Note 10: Recommended operating conditions.
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LTC2142-12/ LTC2141-12/LTC2140-12 TIMING DIAGRAMS
Full Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels
tAP CH 1 ANALOG INPUT A tAP CH 2 ANALOG INPUT B tH tL ENC- ENC+ tD D1_0 - D1_11, OF1 A-6 A-5 A-4 A-3 A-2 B+1 A+1 B+2 B+3 B+4 A+2 A+3 A+4
D2_0 - D2_11, OF2 tC
B-6
B-5
B-4
B-3
B-2
CLKOUT + CLKOUT -
21421012 TD01
Double Data Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels
tAP CH 1 ANALOG INPUT A tAP CH 2 ANALOG INPUT B tH tL ENC- ENC+ tD D1_0_1 BIT 0 A-6 BIT 1 A-6 BIT 0 A-5 tD BIT 1 A-5 BIT 0 A-4 BIT 1 A-4 BIT 0 A-3 BIT 1 A-3 BIT 0 A-2 B+1 A+1 B+2 B+3 B+4 A+2 A+3 A+4
* * *
D1_10_11 BIT 10 A-6 BIT 11 A-6 BIT 10 A-5 BIT 11 A-5 BIT 10 A-4 BIT 11 A-4 BIT 10 A-3 BIT 11 A-3 BIT 10 A-2
D2_0_1
BIT 0 B-6
BIT 1 B-6
BIT 0 B-5
BIT 1 B-5
BIT 0 B-4
BIT 1 B-4
BIT 0 B-3
BIT 1 B-3
BIT 0 B-2
* * *
D2_10_11 BIT 10 B-6 BIT 11 B-6 BIT 10 B-5 BIT 11 B-5 BIT 10 B-4 BIT 11 B-4 BIT 10 B-3 BIT 11 B-3 BIT 10 B-2
OF2_1
OF B-6 tC
OF A-6
OF B-5
OF A-5 tC
OF B-4
OF A-4
OF B-3
OF A-3
OF B-2
CLKOUT+ CLKOUT -
21421012 TD02
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LTC2142-12/ LTC2141-12/LTC2140-12 TIMING DIAGRAMS
Double Data Rate LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels
tAP CH 1 ANALOG INPUT A tAP CH 2 ANALOG INPUT B tH tL ENC- ENC+ D1_0_1+ D1_0_1- D1_10_11+ D1_10_11- D2_0_1+ D2_0_1- D2_10_11+ D2_10_11- OF2_1+ OF2_1- CLKOUT+ CLKOUT - tD BIT 0 A-6 BIT 1 A-6 BIT 0 A-5 tD BIT 1 A-5 BIT 0 A-4 BIT 1 A-4 BIT 0 A-3 BIT 1 A-3 BIT 0 A-2 B+1 A+1 B+2 B+3 B+4 A+2 A+3 A+4
* * *
BIT 10 A-6
BIT 11 A-6
BIT 10 A-5
BIT 11 A-5
BIT 10 A-4
BIT 11 A-4
BIT 10 A-3
BIT 11 A-3
BIT 10 A-2
BIT 0 B-6
BIT 1 B-6
BIT 0 B-5
BIT 1 B-5
BIT 0 B-4
BIT 1 B-4
BIT 0 B-3
BIT 1 B-3
BIT 0 B-2
* * *
BIT 10 B-6
BIT 11 B-6
BIT 10 B-5
BIT 11 B-5
BIT 10 B-4
BIT 11 B-4
BIT 10 B-3
BIT 11 B-3
BIT 10 B-2
OF B-6 tC
OF A-6
OF B-5
OF A-5 tC
OF B-4
OF A-4
OF B-3
OF A-3
OF B-2
21421012 TD03
SPI Port Timing (Readback Mode)
tS CS SCK tDO SDI SDO HIGH IMPEDANCE R/W A6 A5 A4 A3 A2 A1 A0 XX D7 XX D6 XX D5 XX D4 XX D3 XX D2 XX D1 XX D0 tDS tDH tSCK tH
SPI Port Timing (Write Mode)
CS SCK
SDI SDO
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
HIGH IMPEDANCE
21421012 TD04
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LTC2142-12/ LTC2141-12/LTC2140-12 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2142-12: Integral Non-Linearity (INL)
1.0 0.8 0.6 DNL ERROR (LSB) INL ERROR (LSB) 0.4 0.2 0.0 0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 3072 OUTPUT CODE 4096
21421012 G01
LTC2142-12: Differential Non-Linearity (DNL)
1.0 0.8 0.6 AMPLITUDE (dBFS) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 3072 OUTPUT CODE 4096
21421012 G02
LTC2142-12: 64k Point FFT, fIN = 5MHz, -1dBFS, 65Msps
0 -10 -20 -30 -40 -50 -60 -70 -80
-90 -100 -110 -120
0
20 10 FREQUENCY (MHz)
30
21421012 G03
LTC2142-12: 64k Point FFT, fIN = 30MHz, -1dBFS, 65Msps
0 -10 -20 -30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 -50 -60 -70 -80 0 -10 -20 -30 -40 -50 -60 -70 -80
LTC2142-12: 64k Point FFT, fIN = 70MHz, -1dBFS, 65Msps
0 -10 -20 -30 AMPLITUDE (dBFS) 0 20 10 FREQUENCY (MHz) 30
21421012 G05
LTC2142-12: 64k Point FFT, fIN = 140MHz, -1dBFS, 65Msps
-40 -50 -60 -70 -80
-90 -100 -110 -120
-90 -100 -110 -120
-90 -100 -110 -120
0
20 10 FREQUENCY (MHz)
30
21421012 G04
0
20 10 FREQUENCY (MHz)
30
21421012 G06
LTC2142-12: 64k Point 2-Tone FFT fIN = 69MHz 70MHz, FFT, 69MHz, 70MHz -7dBFS, 65Msps
0 -10 -20 -30 AMPLITUDE (dBFS) -40 COUNT -50 -60 -70 -80 14000 12000 10000 8000 6000 4000 2000 0 20 10 FREQUENCY (MHz) 30
21421012 G07
LTC2142-12: Shorted Input Histogram
18000 16000 71 SNR (dBFS) 72
LTC2142-12: SNR vs Input Frequency, -1dBFS, 65Msps, 2V Range
SINGLE-ENDED ENCODE
70 DIFFERENTIAL ENCODE 69
-90 -100 -110 -120
0 2043
2044
2045 2046 OUTPUT CODE
2047
21421012 G08
68
0
50
100 150 200 250 INPUT FREQUENCY (MHz)
300
21421012 G09
21421012p
11
LTC2142-12/ LTC2141-12/LTC2140-12 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2142-12: 2nd, 3rd Harmonic vs Input Frequency, -1dBFS, 65Msps, 2V Range
100 2ND AND 3RD HARMONIC (dBFS) 2ND AND 3RD HARMONIC (dBFS) 95 90 3RD 85 80 75 70 65 100 95 90 85 80 75 70 65 SFDR (dBc AND dBFS) 3RD
LTC2142-12: 2nd, 3rd Harmonic vs Input Frequency, -1dBFS, 65Msps, 1V Range
110 100 90 80 70 60 50 40 30 20 10
LTC2142-12: SFDR vs Input Level, fIN = 70MHz, 65Msps, 2V Range
dBFS
2ND
dBc
2ND
0
50
100 150 200 250 INPUT FREQUENCY (MHz)
300
0
50
100 150 200 250 INPUT FREQUENCY (MHz)
300
0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
21421012 G10
21421012 G11
21421012 G12
LTC2142-12: IVDD vs Sample Rate, 5MHz, -1dBFS Sine Wave Input on Each Channel
55 70 60 50 IVDD (mA) LVDS OUTPUTS IOVDD (mA) 50
LTC2142-12: IOVDD vs Sample Rate, 5MHz, -1dBFS, Sine Wave on Each Channel
72 3.5mA LVDS 71 70 40 30 20 10 1.75mA LVDS
LTC2142-12: SNR vs SENSE, fIN = 5MHz, -1dBFS
45 CMOS OUTPUTS 40
SNR (dBFS) 60
21421012 G14
69 68 67
1.8V CMOS 0 10 20 30 40 50 SAMPLE RATE (Msps) 66 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3
35
0
10
20 30 40 50 SAMPLE RATE (Msps)
60
21421012 G13
0
21421012 G15
LTC2141-12: Integral Non-Linearity (INL)
1.0 0.8 0.6 DNL ERROR (LSB) INL ERROR (LSB) 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 3072 OUTPUT CODE 4096
21421012 G16
LTC2141-12: Differential Non-Linearity (DNL)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 3072 OUTPUT CODE 4096
21421012 G17
LTC2141-12: 64k Point FFT, fIN = 5MHz, -1dBFS, 40Msps
0 -10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80
-90 -100 -110 -120 0 5 10 15 FREQUENCY (MHz) 20
21421012 G18
21421012 21421012p
12
LTC2142-12/ LTC2141-12/LTC2140-12 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2141-12: 64k Point FFT, fIN = 30MHz, -1dBFS, 40Msps
0 -10 -20 -30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 -50 -60 -70 -80 0 -10 -20 -30 -40 -50 -60 -70 -80 AMPLITUDE (dBFS) 0 5 10 15 FREQUENCY (MHz) 20
21421012 G20
LTC2141-12: 64k Point FFT, fIN = 70MHz, -1dBFS, 40Msps
0 -10 -20 -30 -40 -50 -60 -70 -80
LTC2141-12: 64k Point FFT, fIN = 140MHz, -1dBFS, 40Msps
-90 -100 -110 -120 0 5 10 15 FREQUENCY (MHz) 20
21421012 G19
-90 -100 -110 -120
-90 -100 -110 -120 0 5 10 15 FREQUENCY (MHz) 20
21421012 G21
LTC2141-12: 64k Point 2-Tone FFT, fIN = 69MHz, 70MHz, -7dBFS, 40Msps
0 -10 -20 -30 AMPLITUDE (dBFS) -40 COUNT -50 -60 -70 -80 14000 12000 10000 8000 6000 4000 2000 0 5 10 15 FREQUENCY (MHz) 20
21421012 G22
LTC2141-12: Shorted Input Histogram
18000 16000 71 SNR (dBFS) 72
LTC2141-12: SNR vs Input Frequency, -1dBFS, 40Msps, 2V Range
SINGLE-ENDED ENCODE 70 DIFFERENTIAL ENCODE
-90 -100 -110 -120
69
0 2043
2044
2045 2046 OUTPUT CODE
2047
21421012 G23
68
0
50
100 150 200 250 INPUT FREQUENCY (MHz)
300
21421012 G24
LTC2141-12: 2nd, 3rd Harmonic vs Input Frequency, -1dBFS, 40Msps, 2V Range
100 2ND AND 3RD HARMONIC (dBFS) 2ND AND 3RD HARMONIC (dBFS) 95 90 85 80 75 70 65 2ND 3RD 100 95 90 85
LTC2141-12: 2nd, 3rd Harmonic vs Input Frequency, -1dBFS, 40Msps, 1V Range
110 100 90 SFDR (dBc AND dBFS) 3RD 80 70 60 50 40 30 20 10
LTC2141-12: SFDR vs Input Level, fIN = 70MHz, 40Msps, 2V Range
dBFS dBc
2ND 80 75 70 65
0
50
100 150 200 250 INPUT FREQUENCY (MHz)
300
0
50
100 150 200 250 INPUT FREQUENCY (MHz)
300
0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
21421012 G25
21421012 G26
21421012 G27
21421012p
13
LTC2142-12/ LTC2141-12/LTC2140-12 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2141-12: IVDD vs Sample Rate, 5MHz, -1dBFS Sine Wave Input on Each Channel
40 LVDS OUTPUTS 70 60 50 IOVDD (mA) 40 30 20 10 1.8V CMOS 25 0 10 20 30 SAMPLE RATE (Msps) 40
21421012 G28
LTC2141-12: IOVDD vs Sample Rate, 5MHz, -1dBFS, Sine Wave Input on Each Channel
72 3.5mA LVDS 71 70 SNR (dBFS) 69 68 67 66 0 10 20 30 SAMPLE RATE (Msps) 40
21421012 G29
LTC2141-12: SNR vs SENSE, fIN = 5MHz, -1dBFS
35 IVDD (mA)
CMOS OUTPUTS 30
1.75mA LVDS
0
0.6
0.7
0.8
0.9 1 1.1 SENSE PIN (V)
1.2
1.3
21421012 G30
LTC2140-12: Integral Non-Linearity (INL)
1.0 0.8 0.6 0.4 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 3072 OUTPUT CODE 4096
21421012 G31
LTC2140-12: Differential Non-Linearity (DNL)
1.0 0.8 0.6 AMPLITUDE (dBFS) 0 1024 2048 3072 OUTPUT CODE 4096
21421012 G32
LTC2140-12: 64k Point FFT, fIN = 5MHz, -1dBFS, 25Msps
0 -10 -20 -30 -40 -50 -60 -70 -80
DNL ERROR (LSB)
INL ERROR (LSB)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
-90 -100 -110 -120 0 5 FREQUENCY (MHz) 10
21421012 G33
LTC2140-12: 64k Point FFT, fIN = 30MHz, -1dBFS, 25Msps
0 -10 -20 -30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 -50 -60 -70 -80 0 -10 -20 -30 -40 -50 -60 -70 -80
LTC2140-12: 64k Point FFT, fIN = 70MHz, -1dBFS, 25Msps
0 -10 -20 -30 AMPLITUDE (dBFS) 0 5 FREQUENCY (MHz) 10
21421012 G35
LTC2140-12: 64k Point FFT, FFT fIN = 140MHz, -1dBFS, 25Msps
-40 -50 -60 -70 -80
-90 -100 -110 -120 0 5 FREQUENCY (MHz) 10
21421012 G34
-90 -100 -110 -120
-90 -100 -110 -120 0 5 FREQUENCY (MHz) 10
21421012 G36
21421012p
14
LTC2142-12/ LTC2141-12/LTC2140-12 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2140-12: 64k Point 2-Tone FFT, fIN = 69MHz, 70MHz, -7dBFS, 25Msps
0 -10 -20 -30 AMPLITUDE (dBFS) -40 COUNT -50 -60 -70 -80 18000 16000 14000 12000 10000 8000 6000 4000 2000 0 5 FREQUENCY (MHz) 10
21421012 G37
LTC2140-12: Shorted Input Histogram
72
LTC2140-12: SNR vs Input Frequency, -1dBFS, 25Msps, 2V Range
71 SNR (dBFS)
SINGLE-ENDED ENCODE
70
DIFFERENTIAL ENCODE
-90 -100 -110 -120
69
0 2050
68 2051 2052 2053 OUTPUT CODE 2054
21421012 G38
0
50
100 150 200 250 INPUT FREQUENCY (MHz)
300
21421012 G39
LTC2140-12: 2nd, 3rd Harmonic vs Input Frequency, -1dBFS, 25Msps, 2V Range
100 2ND AND 3RD HARMONIC (dBFS) 2ND AND 3RD HARMONIC (dBFS) 95 90 85 80 75 70 65 2ND 3RD 100 95 90 85 80 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300
LTC2140-12: 2nd, 3rd Harmonic vs Input Frequency, -1dBFS, 25Msps, 1V Range
110 100 90 SFDR (dBc AND dBFS) 3RD 80 70 60 50 40 30 20 10 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300
LTC2140-12: SFDR vs Input Level, fIN = 70MHz, 25Msps, 2V Range
dBFS dBc
2ND
0 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS)
0
21421012 G40
21421012 G41
21421012 G42
LTC2140-12: IVDD vs Sample Rate, 5MHz, -1dBFS Sine Wave Input on Each Channel
30 60
LTC2140-12: IOVDD vs Sample Rate, 5MHz, -1dBFS, Sine Wave on Each Input
72 3.5mA LVDS 71 70 1.75mA LVDS SNR (dBFS) 69 68 67 1.8V CMOS 66 0 5 10 15 20 SAMPLE RATE (Msps) 25
LTC2140-12: SNR vs SENSE, fIN = 5MHz, -1dBFS
28
50 LVDS OUTPUTS 40 IOVDD (mA) CMOS OUTPUTS
IVDD (mA)
26
30 20 10 0
24
22
20
0
5
10 15 20 SAMPLE RATE (Msps)
25
0.6
0.7
0.8
0.9 1 1.1 SENSE PIN (V)
1.2
1.3
21421012 G43
21421012 G44
21421012 G45
21421012p
15
LTC2142-12/ LTC2141-12/LTC2140-12 PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT MODES VDD (Pins 1, 16, 17, 64): Analog Power Supply, 1.7V to 1.9V. Bypass to ground with 0.1F ceramic capacitors. Adjacent pins can share a bypass capacitor. VCM1 (Pin 2): Common Mode Bias Output, Nominally Equal to VDD/2. VCM1 should be used to bias the common mode of the analog inputs to channel 1. Bypass to ground with a 0.1F ceramic capacitor. GND (Pins 3, 6, 14): ADC Power Ground. AIN1+ (Pin 4): Channel 1 Positive Differential Analog Input. AIN1- (Pin 5): Channel 1 Negative Differential Analog Input. REFH (Pins 7, 9): ADC High Reference. See the Applications Information section for recommended bypassing circuits for REFH and REFL. REFL (Pins 8, 10): ADC Low Reference. See the Applications Information section for recommended bypassing circuits for REFH and REFL. PAR/SER (Pin 11): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI, SDO become a serial interface that control the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK, SDI, SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or VDD and not be driven by a logic signal. AIN2+ (Pin 12): Channel 2 Positive Differential Analog Input. AIN2- (Pin 13): Channel 2 Negative Differential Analog Input. VCM2 (Pin 15): Common Mode Bias Output, Nominally Equal to VDD/2. VCM2 should be used to bias the common mode of the analog inputs to channel 2. Bypass to ground with a 0.1F ceramic capacitor. ENC+ (Pin 18): Encode Input. Conversion starts on the rising edge. ENC- (Pin 19): Encode Complement Input. Conversion starts on the falling edge. Tie to GND for single-ended encode mode. CS (Pin 20): In Serial Programming Mode, (PAR/SER = 0V), CS Is the Serial Interface Chip Select Input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/SER = VDD), CS controls the clock duty cycle stabilizer (see Table 2). CS can be driven with 1.8V to 3.3V logic. SCK (Pin 21): In Serial Programming Mode, (PAR/SER = 0V), SCK Is the Serial Interface Clock Input. In the parallel programming mode (PAR/SER = VDD), SCK controls the digital output mode (see Table 2). SCK can be driven with 1.8V to 3.3V logic. SDI (Pin 22): In Serial Programming Mode, (PAR/SER = 0V), SDI Is the Serial Interface Data Input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the parallel programming mode (PAR/SER = VDD), SDI can be used together with SDO to power down the part (see Table 2). SDI can be driven with 1.8V to 3.3V logic. OGND (Pin 41): Output Driver Ground. Must be shorted to the ground plane by a very low inductance path. Use multiple vias close to the pin. OVDD (Pin 42): Output Driver Supply. Bypass to ground with a 0.1F ceramic capacitor. SDO (Pin 61): In Serial Programming Mode, (PAR/SER = 0V), SDO Is the Optional Serial Interface Data Output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pull-up resistor to 1.8V - 3.3V. If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In the parallel programming mode (PAR/SER = VDD), SDO can be used together with SDI to power down the part (see Table 2). When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. VREF (Pin 62): Reference Voltage Output. Bypass to ground with a 2.2F ceramic capacitor. The output voltage is nominally 1.25V.
21421012p
16
LTC2142-12/ LTC2141-12/LTC2140-12 PIN FUNCTIONS
SENSE (Pin 63): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a 1V input range. Connecting SENSE to ground selects the internal reference and a 0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of 0.8 * VSENSE. Ground (Exposed Pad Pin 65): The exposed pad must be soldered to the PCB ground. FULL RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND to OVDD) D2_0 to D2_11 (Pins 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38): Channel 2 Digital Outputs. D2_11 is the MSB. DNC (Pins 23, 24, 25, 26, 43, 44, 45, 46): Do not connect these pins. CLKOUT- (Pin 39): Inverted Version of CLKOUT+. CLKOUT+ (Pin 40): Data Output Clock. The digital outputs normally transition at the same time as the falling edge of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. D1_0 to D1_11 (Pins 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58): Channel 1 Digital Outputs. D1_11 Is the MSB. OF2 (Pin 59): Channel 2 Over/Underflow Digital Output. OF2 is high when an overflow or underflow has occurred. OF1 (Pin 60): Channel 1 Over/Underflow Digital Output. OF1 is high when an overflow or underflow has occurred. DOUBLE DATA RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND to OVDD) D2_0_1 to D2_10_11 (Pins 28, 30, 32, 34, 36, 38): Channel 2 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each output pin. The even data bits (D0, D2, D4, D6, D8, D10) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11) appear when CLKOUT+ is high. DNC (Pins 23, 24, 25, 26, 27, 29, 31, 33, 35, 37, 43, 44, 45, 46, 47, 49, 51, 53, 55, 57, 59): Do not connect these pins. CLKOUT- (Pin 39): Inverted Version of CLKOUT+. CLKOUT+ (Pin 40): Data Output Clock. The digital outputs normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. D1_0_1 to D1_10_11 (Pins 48, 50, 52, 54, 56, 58): Channel 1 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each output pin. The even data bits (D0, D2, D4, D6, D8, D10) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11) appear when CLKOUT+ is high. OF2_1 (Pin 60): Over/Underflow Digital Output. OF2_1 is high when an overflow or underflow has occurred. The over/underflow for both channels are multiplexed onto this pin. Channel 2 appears when CLKOUT+ is low, and Channel 1 appears when CLKOUT+ is high. DOUBLE DATA RATE LVDS OUTPUT MODE All Pins Below Have LVDS Output Levels. The Output Current Level Is Programmable. There Is an Optional Internal 100 Termination Resistor Between the Pins of Each LVDS Output Pair. D2_0_1-/D2_0_1+ to D2_10_11-/D2_10_11+ (Pins 27/28, 29/30, 31/32, 33/34, 35/36, 37/38): Channel 2 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (D0, D2, D4, D6, D8, D10) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11) appear when CLKOUT+ is high. CLKOUT-/CLKOUT+ (Pins 39/40): Data Output Clock. The digital outputs normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. DNC (Pins 23, 24, 25, 26, 43, 44, 45, 46): Do not connect these pins.
21421012p
17
LTC2142-12/ LTC2141-12/LTC2140-12 PIN FUNCTIONS
D1_0_1-/D1_0_1+ to D1_10_11-/D1_10_11+ (Pins 47/48, 49/50, 51/52, 53/54, 55/56, 57/58): Channel 2 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (D0, D2, D4, D6, D8, D10) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11) appear when CLKOUT+ is high. OF2_1-/OF2_1+ (Pins 59/60): Over/Underflow Digital Output. OF2_1+ is high when an overflow or underflow has occurred. The over/underflow for both channels are multiplexed onto this pin. Channel 2 appears when CLKOUT+ is low, and Channel 1 appears when CLKOUT+ is high.
FUNCTIONAL BLOCK DIAGRAM
OVDD CH 1 ANALOG INPUT S/H 12-BIT ADC CORE CORRECTION LOGIC CH 2 ANALOG INPUT 12-BIT ADC CORE OF1 OF2 D1_11 * * * D1_0 OUTPUT DRIVERS CLKOUT + CLKOUT - VREF 2.2F 1.25V REFERENCE RANGE SELECT D2_11 * * * D2_0 OGND
S/H
REFH SENSE REF BUF
REFL
INTERNAL CLOCK SIGNALS VDD
VCM1 0.1F VCM2 0.1F
VDD/2
DIFF REF AMP
CLOCK/DUTY CYCLE CONTROL
MODE CONTROL REGISTERS
GND
REFH 2.2F 0.1F
REFL
ENC+
ENC-
PAR/SER CS SCK SDI SDO
21421012 F01
0.1F
Figure 1. Functional Block Diagram
21421012p
18
LTC2142-12/ LTC2141-12/LTC2140-12 APPLICATIONS INFORMATION
CONVERTER OPERATION The LTC2142-12/LTC2141-12/LTC2140-12 are low power, 2-channel, 12-bit, 65Msps/40Msps/25Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially, or single ended for lower power consumption. The digital outputs can be CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system.) Many additional features can be chosen by programming the mode control registers through a serial SPI port. ANALOG INPUT The analog inputs are differential CMOS sample-and-hold circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the VCM1 or VCM2 output pins, which are nominally VDD/2. For the 2V input range, the inputs should swing from VCM - 0.5V to VCM + 0.5V. There should be 180 phase difference between the inputs.
LTC2142-12 VDD 10 CPARASITIC 1.8pF RON 15 CPARASITIC 1.8pF VDD CSAMPLE 5pF RON 15
The two channels are simultaneously sampled by a shared encode circuit (Figure 2). Single-Ended Input For applications less sensitive to harmonic distortion, the AIN+ input can be driven single-ended with a 1VP-P signal centered around VCM. The AIN- input should be connected to VCM. With a single-ended input the harmonic distortion and INL will degrade, but the noise and DNL will remain unchanged. INPUT DRIVE CIRCUITS Input Filtering If possible, there should be an RC lowpass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application's input frequency. Transformer Coupled Circuits
CSAMPLE 5pF
AIN+
VDD 10
AIN-
Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with VCM, setting the A/D input at its optimal DC level. At higher input frequencies, a transmission line balun transformer (Figure 4 to Figure 6) has better balance, resulting in lower A/D distortion.
50 VCM 0.1F
1.2V 10k ENC+
0.1F ANALOG INPUT
T1 1:1 25 25
25 0.1F
AIN+ LTC2142-12 12pF
ENC- 10k 1.2V
21421012 F02
25
AIN-
21421012 F03
T1: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 2. Equivalent Input Circuit. Only One of the Two Analog Channels Is Shown
Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz
21421012p
19
LTC2142-12/ LTC2141-12/LTC2140-12 APPLICATIONS INFORMATION
Amplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is ACcoupled to the A/D so the amplifier's output common mode voltage can be optimally set to minimize distortion. At very high frequencies, an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figure 4 to Figure 6) should convert the signal to differential before driving the A/D.
50 VCM 0.1F 0.1F ANALOG INPUT T2 T1 25 25 12 0.1F 8.2pF 0.1F 12 AIN-
21421012 F04
Reference The LTC2142-12/LTC2141-12/LTC2140-12 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9). The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 * VSENSE. The VREF, REFH and REFL pins should be bypassed, as shown in Figure 8. A low inductance 2.2F interdigitated capacitor is recommended for the bypass between REFH and REFL. This type of capacitor is available at a low cost from multiple suppliers.
50 VCM 0.1F 0.1F ANALOG INPUT T1 4.7nH 25 25 0.1F AIN+ LTC2142-12
AIN+ LTC2142-12
T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1TL RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 4. Recommended Front-End Circuit for Input Frequencies from 5MHz to 150MHz
0.1F
4.7nH
AIN-
21421012 F06
T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 50 VCM 0.1F 0.1F ANALOG INPUT T2 T1 25 25 0.1F 1.8pF 0.1F AIN-
21421012 F05
AIN+ LTC2142-12
Figure 6. Recommended Front-End Circuit for Input Frequencies Above 250MHz
VCM HIGH SPEED DIFFERENTIAL 0.1F AMPLIFIER ANALOG INPUT 200 200 25 0.1F AIN+ 12pF 0.1F LTC2142-12
+ -
T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1TL RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
+ -
25
AIN- 12pF
21421012 F07
Figure 5. Recommended Front-End Circuit for Input Frequencies from 150MHz to 250MHz
Figure 7. Front-End Circuit Using a High Speed Differential Amplifier
21421012p
20
LTC2142-12/ LTC2141-12/LTC2140-12 APPLICATIONS INFORMATION
LTC2142-12 1.25V VREF 2.2F 0.625V RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE C2 0.1F 5 1.25V BANDGAP REFERENCE
REFL pins are connected by short jumpers in an internal layer. To minimize the inductance of these jumpers they can be placed in a small hole in the GND plane on the second board layer.
TIE TO VDD FOR 2V RANGE; TIE TO GND FOR 1V RANGE; SENSE FOR 0.625V < VSENSE < 1.300V
- +
C1
+ - + -
REFH REFL 0.8x DIFF AMP
Figure 8c. Recommended Layout for the REFH/REFL Bypass Circuit in Figure 8a
-
C3 0.1F
REFH REFL
+
INTERNAL ADC LOW REFERENCE C1: 2.2F LOW INDUCTANCE INTERDIGITATED CAPACITOR TDK CLLE1AX7S0G225M MURATA LLA219C70G225M AVX W2L14Z225M OR EQUIVALENT
21421012 F08a
Figure 8d. Recommended Layout for the REFH/REFL Bypass Circuit in Figure 8b
VREF 2.2F LTC2142-12 1.25V EXTERNAL REFERENCE SENSE 1F
21421012 F09
Figure 8a. Reference Circuit
Alternatively C1 can be replaced by a standard 2.2F capacitor between REFH and REFL (see Figure 8b). The capacitors should be as close to the pins as possible (not on the back side of the circuit board). Figure 8c and Figure 8d show the recommended circuit board layout for the REFH/REFL bypass capacitors. Note that in Figure 8c, every pin of the interdigitated capacitor (C1) is connected since the pins are not internally connected in some vendors' capacitors. In Figure 8d the REFH and
C3 0.1F C1 2.2F C2 0.1F REFH REFL LTC2142-12
Figure 9. Using an External 1.25V Reference
Encode Inputs The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals - do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10), and the single-ended encode mode (Figure 11). The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figure 12 and Figure 13). The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode,
21421012p
REFH REFL
21421012 F08b
CAPACITORS ARE 0402 PACKAGE SIZE
Figure 8b. Alternative REFH/REFL Bypass Circuit
21
LTC2142-12/ LTC2141-12/LTC2140-12 APPLICATIONS INFORMATION
LTC2142-12 VDD DIFFERENTIAL COMPARATOR
VDD
ENC- should stay at least 200mV above ground to avoid falsely triggering the single ended encode mode. For good jitter performance ENC+ and ENC- should have fast rise and fall times. The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC- is connected to ground and ENC+ is driven with a square wave encode input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance, ENC+ should have fast rise and fall times. If the encode signal is turned off or drops below approximately 500kHz, the A/D enters nap mode. Clock Duty Cycle Stabilizer For good performance the encode signal should have a 50% (5%) duty cycle. If the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the encode signal changes frequency, the duty cycle stabilizer circuit requires one hundred clock cycles to lock onto the input clock. The duty cycle stabilizer is enabled by mode control register A2 (serial programming mode), or by CS (parallel programming mode). For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (5%) duty cycle. The duty cycle stabilizer should not be used below 5Msps. DIGITAL OUTPUTS Digital Output Modes
15k ENC+ ENC- 30k
21421012 F10
Figure 10. Equivalent Encode Input Circuit for Differential Encode Mode
LTC2142-12 1.8V TO 3.3V 0V ENC+ ENC- 30k CMOS LOGIC BUFFER
21421012 F11
Figure 11. Equivalent Encode Input Circuit for Single-Ended Encode Mode
0.1F T1
ENC+ 50 100 LTC2142-12
0.1F
50 ENC-
21421012 F12
0.1F T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE
Figure 12. Sinusoidal Encode Drive
0.1F
ENC+
PECL OR LVDS CLOCK
LTC2142-12 0.1F ENC-
21421012 F13
Figure 13. PECL or LVDS Encode Drive
The LTC2142-12/LTC2141-12/LTC2140-12 can operate in three digital output modes: full rate CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system.) The output mode is set by mode control register A3 (serial programming mode), or by SCK (parallel programming mode). Note that double data rate CMOS cannot be selected in the parallel programming mode.
21421012p
22
LTC2142-12/ LTC2141-12/LTC2140-12 APPLICATIONS INFORMATION
Full Rate CMOS Mode In full rate CMOS mode the data outputs (D1_0 to D1_11 and D2_0 to D2_11), overflow (OF2, OF1), and the data output clocks (CLKOUT+, CLKOUT-) have CMOS output levels. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. OVDD can range from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs. For good performance, the digital outputs should drive minimal capacitive loads. If the load capacitance is larger than 10pF a digital buffer should be used. Double Data Rate CMOS Mode In double data rate CMOS mode, two data bits are multiplexed and output on each data pin. This reduces the number of digital lines by thirteen, simplifying board routing and reducing the number of input pins needed to receive the data. The data outputs (D1_0_1, D1_2_3, D1_4_5, D1_6_7, D1_8_9, D1_10_11, D2_0_1, D2_2_3, D2_4_5, D2_6_7, D2_8_9, D2_10_11), overflow (OF2_1), and the data output clocks (CLKOUT+, CLKOUT-) have CMOS output levels. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. OVDD can range from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs. Note that the overflow for both ADC channels is multiplexed onto the OF2_1 pin. For good performance, the digital outputs should drive minimal capacitive loads. If the load capacitance is larger than 10pF a digital buffer should be used. Double Data Rate LVDS Mode In double data rate LVDS mode, two data bits are multiplexed and output on each differential output pair. There are six LVDS output pairs per ADC channel (D1_0_1+/D1_0_1- through D1_10_11+/D1_10_11- and D2_0_1+/D2_0_1- through D2_10_11+/D2_10_11-) for the digital output data. Overflow (OF2_1+/OF2_1-) and the data output clock (CLKOUT+/CLKOUT-) each have an LVDS output pair. Note that the overflow for both ADC channels is multiplexed onto the OF2_1+/OF2_1- output pair. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage. An external 100 differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. In LVDS mode, OVDD must be 1.8V. Programmable LVDS Output Current In LVDS mode, the default output driver current is 3.5mA. This current can be adjusted by serially programming mode control register A3. Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. Optional LVDS Driver Internal Termination In most cases, using just an external 100 termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100 termination resistor can be enabled by serially programming mode control register A3. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. Overflow Bit The overflow output bit outputs a logic high when the analog input is either overranged or underranged. The overflow bit has the same pipeline latency as the data bits. In full rate CMOS mode each ADC channel has its own overflow pin (OF1 for channel 1, OF2 for channel 2). In DDR CMOS or DDR LVDS mode the overflow for both ADC channels is multiplexed onto the OF2_1 output.
21421012p
23
LTC2142-12/ LTC2141-12/LTC2140-12 APPLICATIONS INFORMATION
Phase Shifting the Output Clock In full rate CMOS mode the data output bits normally change at the same time as the falling edge of CLKOUT+, so the rising edge of CLKOUT+ can be used to latch the output data. In double data rate CMOS and LVDS modes the data output bits normally change at the same time as the falling and rising edges of CLKOUT+. To allow adequate set-up and hold time when latching the data, the CLKOUT+ signal may need to be phase shifted relative to the data output bits. Most FPGAs have this feature; this is generally the best place to adjust the timing. The LTC2142-12/LTC2141-12/LTC2140-12 can also phase shift the CLKOUT+/CLKOUT- signals by serially programming mode control register A2. The output clock can be shifted by 0, 45, 90, or 135. To use the phase shifting feature the clock duty cycle stabilizer must be turned on. Another control register bit can invert the polarity of CLKOUT+ and CLKOUT-, independently of the phase shift. The combination of these two features enables phase shifts of 45 up to 315 (Figure 14).
ENC+
DATA FORMAT Table 1 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. By default the output data format is offset binary. The 2's complement format can be selected by serially programming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ - AIN- (2V Range) >+1.000000V +0.999512V +0.999024V +0.000488V 0.000000V -0.000488V -0.000976V -0.999512V -1.000000V -1.000000V OF 1 0 0 0 0 0 0 0 0 1 D11-D0 (OFFSET BINARY) 1111 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 0000 0000 0000 D11-D0 (2's COMPLEMENT) 0111 1111 1111 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 1000 0000 0000
D0-D11, OF PHASE SHIFT 0 45 90 135 CLKOUT+ 180 225 270 315
21421012 F14
MODE CONTROL BITS CLKINV 0 0 0 0 1 1 1 1 CLKPHASE1 0 0 1 1 0 0 1 1 CLKPHASE0 0 1 0 1 0 1 0 1
Figure 14. Phase Shifting CLKOUT
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24
LTC2142-12/ LTC2141-12/LTC2140-12 APPLICATIONS INFORMATION
Digital Output Randomizer Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. The digital output is randomized by applying an exclusiveOR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied - an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output randomizer is enabled by serially programming mode control register A4. Alternate Bit Polarity Another feature that reduces digital feedback on the circuit board is the alternate bit polarity mode. When this mode is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11) are inverted before the output buffers. The even bits (D0, D2, D4, D6, D8, D10), OF and CLKOUT are not affected. This can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for very small analog input signals. When there is a very small signal at the input of the A/D that is centered around mid-scale, the digital outputs toggle between mostly 1's and mostly 0's. This simultaneous switching of most of the bits will cause large currents in the ground plane. By inverting every other bit, the alternate bit polarity mode makes half of the bits transition high while half of the bits transition low. This cancels current flow in the ground plane, reducing the digital noise. The digital output is decoded at the receiver by inverting the odd bits (D1, D3, D5, D7, D9, D11). The alternate bit polarity mode is independent of the digital output randomizer - either, both or neither function can be on at the same time. The alternate bit polarity mode is enabled by serially programming mode control register A4.
CLKOUT CLKOUT
OF
OF
D11
D11/D0
D10
D10/D0
D2 RANDOMIZER ON D1
* * *
D2/D0
D1/D0
D0
D0
21421012 F15
Figure 15. Functional Equivalent of Digital Output Randomizer
PC BOARD CLKOUT FPGA
OF
D11/D0 D11 D10/D0 LTC2142-12 D2/D0 D2 D1/D0 D1 D0 D0
21421012 F16
D10
Figure 16. Unrandomizing a Randomized Digital Output Signal
21421012p
25
LTC2142-12/ LTC2141-12/LTC2140-12 APPLICATIONS INFORMATION
Digital Output Test Patterns To allow in-circuit testing of the digital interface to the A/D, there are several test modes that force the A/D data outputs (OF D11-D0) to known values: , All 1s: All outputs are 1 All 0s: All outputs are 0 Alternating: Outputs change from all 1s to all 0s on alternating samples. Checkerboard: Outputs change from 1010101010101 to 0101010101010 on alternating samples. The digital output test patterns are enabled by serially programming mode control register A4. When enabled, the test patterns override all other formatting modes: 2's complement, randomizer, alternate bit polarity. Output Disable The digital outputs may be disabled by serially programming mode control register A3. All digital outputs including OF and CLKOUT are disabled. The high impedance disabled state is intended for in-circuit testing or long periods of inactivity - it is too slow to multiplex a data bus between multiple converters at full speed. When the outputs are disabled both channels should be put into either sleep or nap mode. Sleep and Nap Modes The A/D may be placed in sleep or nap modes to conserve power. In sleep mode the entire device is powered down, resulting in 1mW power consumption. The amount of time required to recover from sleep mode depends on the size of the bypass capacitors on VREF, REFH, and REFL. For the suggested values in Fig. 8, the A/D will stabilize after 2ms. In nap mode the A/D core is powered down while the internal reference circuits stay active, allowing faster wakeup than from sleep mode. Recovering from nap mode requires at least 100 clock cycles. If the application demands very accurate DC settling then an additional 50s should be allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current as the A/D leaves nap mode. Either channel 2 or both channels can be placed in nap mode; it is not possible to have channel 1 in nap mode and channel 2 operating normally. Sleep mode and nap mode are enabled by mode control register A1 (serial programming mode), or by SDI and SDO (parallel programming mode). DEVICE PROGRAMMING MODES The operating modes of the LTC2142-12/LTC2141-12/ LTC2140-12 can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes. Parallel Programming Mode To use the parallel programming mode, PAR/SER should be tied to VDD. The CS, SCK, SDI and SDO pins are binary logic inputs that set certain operating modes. These pins can be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V CMOS logic. When used as an input, SDO should be driven through a 1k series resistor. Table 2 shows the modes set by CS, SCK, SDI and SDO.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN CS DESCRIPTION Clock Duty Cycle Stabilizer Control Bit 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On SCK Digital Output Mode Control Bit 0 = Full Rate CMOS Output Mode 1 = Double Data Rate LVDS Output Mode (3.5mA LVDS Current, Internal Termination Off) SDI/SDO Power Down Control Bit 00 = Normal Operation 01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode 10 = Channel 1 and Channel 2 in Nap Mode 11 = Sleep Mode (Entire Device Powered Down)
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26
LTC2142-12/ LTC2141-12/LTC2140-12 APPLICATIONS INFORMATION
Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address bits (A6:A0) will be read back on the SDO pin (see the timing diagrams). During a read back command the register is not updated and data on SDI is ignored. The SDO pin is an open drain output that pulls to ground with a 200 impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and read back is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 3 shows a map of the mode control registers. Software Reset If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset is complete, bit D7 is automatically set back to zero. GROUNDING AND BYPASSING The LTC2142-12/LTC2141-12/LTC2140-12 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane in the first layer beneath the ADC is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass capacitors must be located as close to the pins as possible. Size 0402 ceramic capacitors are recommended. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. Of particular importance is the capacitor between REFH and REFL. This capacitor should be on the same side of the circuit board as the A/D, and as close to the device as possible. The analog inputs, encode signals, and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. HEAT TRANSFER Most of the heat generated by the LTC2142-12/LTC2141-12/ LTC2140-12 is transferred from the die through the bottomside exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. This pad should be connected to the internal ground planes by an array of vias.
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27
LTC2142-12/ LTC2141-12/LTC2140-12 APPLICATIONS INFORMATION
Table 3. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h) D7 RESET Bit 7 RESET 0 = Not Used 1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode. This Bit Is Automatically Set Back to Zero After the Reset Is Complete Bits 6-0 Unused, Don't Care Bits. D6 X D5 X Software Reset Bit D4 X D3 X D2 X D1 X D0 X
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h) D7 X Bits 7-2 Bits 1-0 D6 X Unused, Don't Care Bits. PWROFF1:PWROFF0 00 = Normal Operation 01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode 10 = Channel 1 and Channel 2 in Nap Mode 11 = Sleep Mode REGISTER A2: TIMING REGISTER (ADDRESS 02h) D7 X Bits 7-4 Bit 3 D6 X Unused, Don't Care Bits. CLKINV Output Clock Invert Bit 0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams) 1 = Inverted CLKOUT Polarity Bits 2-1 CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits 00 = No CLKOUT Delay (As Shown in the Timing Diagrams) 01 = CLKOUT+/CLKOUT- Delayed by 45 (Clock Period * 1/8) 10 = CLKOUT+/CLKOUT- Delayed by 90 (Clock Period * 1/4) 11 = CLKOUT+/CLKOUT- Delayed by 135 (Clock Period * 3/8) Note: If the CLKOUT Phase Delay Feature Is Used, the Clock Duty Cycle Stabilizer Must Also Be Turned On Bit 0 DCS Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On D5 X D4 X D3 CLKINV D2 CLKPHASE1 D1 CLKPHASE0 D0 DCS Power Down Control Bits D5 X D4 X D3 X D2 X D1 PWROFF1 D0 PWROFF0
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LTC2142-12/ LTC2141-12/LTC2140-12 APPLICATIONS INFORMATION
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h) D7 X Bit 7 Bits 6-4 D6 ILVDS2 Unused, Don't Care Bit. ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current is 2 the Current Set by ILVDS2:ILVDS0 OUTOFF Output Disable Bit 0 = Digital Outputs Are Enabled 1 = Digital Outputs Are Disabled and Have High Output Impedance Note: If the Digital Outputs Are Disabled the Part Should Also Be Put in Sleep or Nap Mode (Both Channels). OUTMODE1:OUTMODE0 Digital Output Mode Control Bits 00 = Full Rate CMOS Output Mode 01 = Double Data Rate LVDS Output Mode 10 = Double Data Rate CMOS Output Mode 11 = Not Used D5 ILVDS1 D4 ILVDS0 D3 TERMON D2 OUTOFF D1 OUTMODE1 D0 OUTMODE0
Bit 3
Bit 2
Bits 1-0
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h) D7 X Bit 7-6 Bits 5-3 D6 X Unused, Don't Care Bits. OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits 000 = Digital Output Test Patterns Off 001 = All Digital Outputs = 0 011 = All Digital Outputs = 1 101 = Checkerboard Output Pattern. OF D11-D0 Alternate Between 1 0101 0101 0101 and 0 1010 1010 1010 , 111 = Alternating Output Pattern. OF D11-D0 Alternate Between 0 0000 0000 0000 and 1 1111 1111 1111 , Note: Other Bit Combinations Are Not Used ABP Alternate Bit Polarity Mode Control Bit 0 = Alternate Bit Polarity Mode Off 1 = Alternate Bit Polarity Mode On. Forces the Output Format to Be Offset Binary RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On TWOSCOMP Two's Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two's Complement Data Format
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D5 OUTTEST2
D4 OUTTEST1
D3 OUTTEST0
D2 ABP
D1 RAND
D0 TWOSCOMP
Bit 2
Bit 1
Bit 0
29
LTC2142-12/ LTC2141-12/LTC2140-12 TYPICAL APPLICATIONS
Silkscreen Top
Top Side
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30
LTC2142-12/ LTC2141-12/LTC2140-12 TYPICAL APPLICATIONS
Inner Layer 2 GND
Inner Layer 3
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31
LTC2142-12/ LTC2141-12/LTC2140-12 TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5 Power
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32
LTC2142-12/ LTC2141-12/LTC2140-12 TYPICAL APPLICATIONS
Bottom Side
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33
LTC2142-12/ LTC2141-12/LTC2140-12 TYPICAL APPLICATIONS
SDO C23 2.2F SENSE VDD C19 C20 0.1F 0.1F 64 63 62 61 60 59 58 57 56 55 54 53 52 51 D1_4_5- 50 D1_2_3+ 49 D1_2_3-
C17 1F
VDD
SENSE
VREF
SDO
OF2_1+
OF2_1-
D1_10_11+
D1_10_11-
D1_8_9+
D1_8_9-
D1_6_7+
D1_6_7-
D1_4_5+
1 2 3 AIN1 AIN1 C15 0.1F
+ -
VDD VCM1 GND AIN1
+
D1_0_1+ D1_0_1- DNC DNC DNC DNC OVDD OGND CLKOUT+ CLKOUT- D2_10_11+ D2_10_11- D2_8_9+ D2_8_9- D2_6_7+ D2_6_7-
-
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 65
DIGITAL OUTPUTS
4 5 6 7 8 9 10 11 12 13 14 15 16
AIN1- GND REFH REFL REFH REFL PAR/SER AIN2
+
- +
CN1
+ - + -
LTC2142-12
C37 0.1F
OVDD
C21 0.1F
- +
AIN2- GND VCM2 VDD D2_1_0+ D2_2_3- D2_2_3+ D2_4_5- D2_4_5+ D2_1_0 ENC+ ENC- DNC DNC DNC DNC SCK
DIGITAL OUTPUTS
PAR/SER AIN2+ AIN2- VDD C67 0.1F
VDD
17
18
19
20
21
22
SDI
PAD
CS
23
24
25
26
27
28
29
30
31
C18 0.1F C78 0.1F C79 0.1F R51 100
21821012 TA02
ENCODE CLOCK
32
SPI BUS
LTC2142 Schematic
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34
LTC2142-12/ LTC2141-12/LTC2140-12 PACKAGE DESCRIPTION
UP Package 64-Lead Plastic QFN (9mm x 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
0.70 0.05
7.15 0.05
7.50 REF 8.10 0.05 9.50 0.05 (4 SIDES)
7.15 0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 9 .00 0.10 (4 SIDES) 0.75 0.05 R = 0.115 TYP
R = 0.10 TYP
63 64 0.40 0.10 1 2 PIN 1 CHAMFER C = 0.35
PIN 1 TOP MARK (SEE NOTE 5)
7.15 0.10 7.50 REF (4-SIDES)
7.15 0.10
(UP64) QFN 0406 REV C
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE
0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LINEAR TECHNOLOGY CONFIDENTIAL LTC2142-12/ LTC2141-12/LTC2140-12 TYPICAL APPLICATIONS
1.8V VDD 1.8V OVDD 0 -10 CH 1 ANALOG INPUT -20 AMPLITUDE (dBFS) S/H 12-BIT ADC CORE D1_11 * * * D1_0 OUTPUT DRIVERS D2_11 * * * D2_0 -30 -40 -50 -60 -70 -80 CMOS OR LVDS OUTPUTS
2-Tone FFT, fIN = 70MHz and 69MHz
CH 2 ANALOG INPUT
S/H
12-BIT ADC CORE
-90 -100 -110 -120
125MHz CLOCK GND
CLOCK CONTROL
21454312 TA01a
0
20 10 FREQUENCY (MHz)
30
21821012 TA01b
OGND
RELATED PARTS
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800MHz, 31dB Range, Analog-Controlled Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure, Variable Gain Amplifier 4mm x 4mm QFN-24 Dual Matched 7MHz/10MHz/14MHz Filters with ADC Drivers Dual Matched 2nd Order Lowpass Filters with Differential Drivers, Pin-Programmable Gain, 6mm x 3mm DFN-22 Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers
21421012p
36 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0311 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2011

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